In modern integrated circuits (“ICs”), reduction of feature sizes is an important consideration in reducing the manufacturing cost. A likewise important consideration is the speed that stored data may be read. The speed of a memory IC depends, among others, on the speed of word lines. In the semiconductor industry's continued effort to reduce feature sizes of ICs, the width of word lines is also reduced, which increases the resistance of the word lines. As is known, higher resistance on a word line reduces its speed, which, in turn, decreases the speed of the memory IC.
In order to fabricate high performance ICs, low resistivity on the word line is therefore critical. In conventional metal-oxide semiconductor (“MOS”) ICs, polysilicon is often used in place of aluminum (Al) as the gate material. However, a drawback of polysilicon compared to aluminum is its significantly higher resistivity, which may be reduced by doping. Nevertheless, even when doped at a high concentration, the resistance of doped polysilicon remains high. One approach to reduce polysilicon resistivity is to deposit a layer of metal over the polysilicon, or the gate area of a CMOS transistor after the CMOS transistor has been formed. Only the portion of the metal layer deposited over the polysilicon layer will react with the polysilicon to form silicide. The process for forming suicides is therefore “self-aligned” and is referred to as the salicide technology. Through the formation of a metal silicide layer over a polysilicon gate, the resulting “polycide” has a significantly lower resistivity. Common metals used for the formation of polycide structures include, but are not limited to, titanium, tungsten, molybdenum, and cobalt.
Polycide formation is typically followed by a high temperature anneal process to further reduce the electrical resistance of the polycide layer. However, the thermal annealing may lead to the diffusion of silicon atoms from the polysilicon layer and into the overlying gate polycide structure. Such a diffusion creates voids at the polycide/polysilicon interface and may adversely affect the operations of the ICs.